Virage Logic Open Positions

Virage Logic India is hiring for various positions mentioned below.

Please check the following site for contact details and send your resume.

www.viragelogic.com

We are looking at hiring for following positions:

1.      Memory Circuit Designer (Noida)

Memory Circuit Designer will be required to design, develop & validate high performance CMOS SRAM/ ROM/CAM circuits & embedded memory compilers. She/he would be expected to work with minimal supervision on memory design projects from specification to final delivery.

 

Requirements:

·         Experience of compiler modules for CMOS SRAM memories, including physical tiling, netlist generation, timing analysis and front end model generation.

·         Should be experienced with circuit design, IC layout, UNIX scripts, and CAD verification.

·         Solid CMOS design fundamentals

·         Knowledge of design principles and practices

·         Understanding of semi-conductor design and manufacturing

·         Proficient in DRC/LVS/parasitic extraction/Spice simulations

·         Understanding of SRAM/ROM architecture

·         Understanding of key SRAM blocks viz. Sense Amplifiers, Row Decoders, IOs etc

·         Should be able work as a team towards the completion of a memory project

·         Knowledge of sub micron design issues

·         knowledgeable in design rule analysis, parasitic extraction, noise & crosstalk issues, yield improvement and manufacturability issues and design for test principles

 

Experience:     Should have at least 4 – 5 years experience in memory design

Qualification: Should have at least a Bachelors degree in Electronics Engineering.

 

2.      Physical Design (Layout) Engineer (Noida)

Physical Design Engineer will be required to contribute towards backend design for customer projects, support in revising and debugging existing products, create relevant documentation for company products, and run product QA and resolve issues thereof. This person will also be required to understand the memory compiler development and methodology.

 

Requirements

·         Fundamentals of CMOS, Fabrication Methodology.

·         Knowledge of physical design methodologies/ Physical design phases: Floor planning, Place and route, physical verification, Signal integrity.

·         Tools: Sign-off quality tools in each design phase. Have solid knowledge of design principles and practices.

·         Work with moderate supervision. Have working knowledge of basic design tools with some knowledge of advanced design tools. Produce technical design documents and maintain accurate and thorough documentation of work. Be a positive participant, cultivator and active team member.

·         Apply basic to moderate problem solving skills. Able to do project status reporting.

·         Have basic task tracking and self-management skills.

 

Experience:     Should have at least 3 – 4 years experience in memory full custom design

Qualification: Should have at least a Bachelors degree in Electronics Engineering.

3.      Lead DDR Design Engineer (Pune)

The Lead DDR Design Engineer will be required to:

·         Lead the end to end development and productization of IP cores

·         Develop architecture, micro architecture and specifications for IP cores in consultation with marketing and customers

·         Articulate the technical value and benefits of our products to customers in the context of the customers’ application.

·         Review the design, verification, layout, and all collateral for the product and provide direction to the team to ensure quality and competitiveness

·         Take over existing IP core products and manage their development and productization

 

Requirements

·         In depth knowledge of DDR Controller, arbiter, PHY and related standards is MUST.

·         Minimum BS EE/CS required, MS preferred, plus 5 or more years of relevant engineering experience.

·         Experience with design of major portions of multiple successful ASIC/SoC designs

·         Strong logic design, clock domain crossings, synthesis, functional and timing verification skills

·         The ideal candidate will be familiar with all stages in the ASIC design flow including DFT, timing analysis, floor planning, ECO flow, silicon bring-up, and ATE test support.

·         Flexible, creative, and able to perform high quality work independently with minimal supervision.

·         Team player with excellent written and verbal communications skills

 

Experience:     Should have at least 5 years experience

Qualification: Minimum BS EE/CS required, MS preferred

 

4.      DDR Design Engineer (Pune)

The DDR Design Engineer would be responsible for RTL design, Logic verification, Synthesis and timing closure.

·         Experience in RTL logic design using verilog and industry standard tools EDA tools such Synopsys Design Compiler, VCS, NC-SIM etc.

·         Ability to analyze timing using Primetime

·         Experience with complete FPGA and ASIC Flows involving timing closure of High Speed Digital Design

·         Using scripting languages and design automation

·         Good communication, interpersonal skills, team motivator and team player.

 

Experience:     Should have over 3 years experience in ASIC design.

Qualification: Bachelors or Masters Degree in electronics or electrical engineering (BSEE or MSEE) or equivalent from reputed universities.

 

 

5.      Lead Verification Engineer (Pune)

The Lead Verification Engineer will be required to:

·         Lead the end to end development and productization of IP cores

·         Develop test plan from specification, design verification infrastructure and execute exhaustive logic verification

·         Key application areas would include DDR memory controller, arbiter and DDR PHY

·         Responsible for developing verification test benches, monitors and score-board test cases, RTL & gate netlist verification.

·         Assisting the design team for fixing bugs and making customer releases.

·         Mentor and guide junior engineers and taking existing IP core products and manages their development and productization.

 

Requirements

·         In depth knowledge of scripting knowledge, developing simulation test benches, writing PLI routines and running simulations using VCS, NC-simulator, modelsim.

·         Minimum BS EE/CS required, MS preferred, plus 5 or more years of relevant engineering experience.

·         Experience with System Verilog and/or Specman-e test languages and formal verification tools

·         Experience in developing constrained random based test environments

·         Excellent analysis and debugging skills.

·         Team motivator with excellent written and verbal communications skills

 

Experience:     Should have at least 5 years experience

Qualification: Minimum BS EE/CS required, MS preferred

 

6.      Verification Engineer (Pune)

The Verification Engineer would be responsible for developing test plan from specification, design verification infrastructure and execute exhaustive logic verification

·         Key application areas would include DDR memory controller, arbiter and DDR PHY

·         Responsible for developing verification test benches, monitors and score-board test cases, RTL & gate netlist verification.

·         Assisting the design team for fixing bugs.

·         Take over existing IP products and manages their verification infrastructure.

 

Requirements

·         Versatile with scripting knowledge, developing simulation test benches, writing PLI routines and running simulations using VCS, NC-simulator, modelsim.

·         Minimum BS EE/CS required, having minimum 3 or more years of relevant engineering experience.

·         Experience with System Verilog and/or Specman-e test languages and formal verification tools

·         Experience in developing constrained random based test environments

·         Excellent analysis and debugging skills.

·         Good communication and interpersonal skills and team player

 

Experience:     Should have at least 3 years experience

Qualification: Bachelors or Masters Degree in electronics or electrical engineering (BSEE or MSEE) or equivalent from reputed universities.

 

7.      Lead CAD Engineer (Pune)

The CAD engineer will be involved in the development and support of CAD tools, flows and methodology. Essential duties and responsibilities will involve: 

·        Development of CAD Tools, Flows, Methodology

·        Daily CAD Support Activities

·        Development and Support of Technology Library for internal development 

 

Requirements

·        Expert level in scripting languages like Perl, Tcl

·        Expertise in Cadence Custom IC Tools

·        Analog Design Environment (ADE) Flow

·        Virtuoso-XL, CCAR,

·        Spectre, AMS, UltraSim 

·        Proficient in SKILL/Ocean programming language

·        Good understanding of overall circuit simulation flow/methodology

 

Experience: Should have at least 6+ years experience in CAD
Education: Bachelor’s or Masters Degree in electronics or electrical engineering (BSEE or MSEE) or equivalent from reputed universities.