IBM Referral Openings | IBM Walk In | IBM Bangalore Jobs

Friday, May 27, 2011





















Dear All: 

At IBM India, Diversity is a key ingredient that unlocks the potential for excellence in our people. And in this diverse ecosystem, women IBMers have diverse roles and hold highly visible positions of significant responsibility, ranging from profit and loss responsibility to product development. 

Here is your opportunity to encourage and inspire women professionals to join our diverse workforce at IBM India and grow their careers in an inclusive work environment. 

We have the Diversity event for 2011 scheduled on June 11, 2011 : Saturday in Bangalore. 

Request you to share referrals and be part of this Exclusive Diversity Event & be eligible for Referral Bonus!!! 




Job CodeJob DescriptionRelavent ExpTotal ExpJob Location
STG-0389302SSTA Tool Development Engineer  
JD: IBM EDA Team develops tools and flows for Statistical Static Timing, Functional Verification, Physical Design, Synthesis and DFT for high-end microprocessor designs. This position requires the person to setup a mission focused statistical development team in IBM Bangalore. Intially, the candidate is expected to do individual contribution towards product development working along w/ global development and research teams. If the candidate has capability, there are opportunities to collaborate with premier universities in India in research work in statistical timing analysis. 
Skills: Prior experience in working with Static timing analysis tools and flows - Understanding complexities of design process at advanced process nodes (DFM, Variation etc etc..) - Strong scripting skills and prior experience of working with design flows.
7+ yrs7+ yrsBangalore
STG-0389303Physical Design Methodology Engineer 
JD: The position requires working with cutting edge (32/22nm) physical design tools and developing methodologies for Processors. Support to our internal physical designers would be integral part of this role. 
Skill: Person should have experience with hierarchical and datapath floorplans, placement, routing, parasitic extraction, DRC, LVS as well as technology scaling. Prior experience with formal verification and transistor-level power analysis would be a plus. Need working knowledge and experience in writing methodological support scripts in SKILL or TCL, text file parsing and reporting using Perl or sed/awk, and batch execution in Unix shells.
7+ yrs7+ yrsBangalore
STG-0389302 DFT Engineer 
JD: The candidate will be responsible to lead in areas of ASIC and Custom logic test methodologies for advanced technologies with emphasis on Design-for-Test synthesis, memory and logic test structure insertion and validation. The candidate will work on industry leading test methodologies involving IBM automation and vendor logic synthesis and verification tools. Work also includes design of test structures, verilog simulation, test structure verification, enablement and support of customers. Candidate must have strong understanding of digital logic design, extensive experience in working with real designs, especially in the area of muxscan style. The candindate should have a good working knowledge of at-speed test, Array Built-In SelfTest (ABIST), Logic Built-In Self Test (LBIST), and In-System Test. 
Skills: Design-for-Test - Digital Logic Design - Cadence RTL Compiler, Build Top Shell, Encounter Test - IEEE 1149 JTAG standard - Programming and scripting skills (Verilog, Tcl, Xml) - Strong teamwork and communication skills - Extensive working knowledge on real designs in both applying and debugging DFT techniques.
7+ yrs7+ yrsBangalore
STG-0389303Manager Verification Tools
JD: The person hired for this position will have people management responsibility for a small team of 5 engineers working on IBM verification tools and methodologies for complex processors. The managers primary responsibilities will be to grow the team through top notch hiring and managing existing projects. The manager will be expected to regularly interlock with US management to understand deliverables and ensure smooth execution of projects. The manager may also have to provide technical leadership to some of the sub-teams. Manager is responsible for team morale, retention and hiring.
Skills: Needs to have strong background in verification tools and technologies for complex processor designs. People management skills. Managing stake holders. Project management.
7+ yrs7+ yrsBangalore






Job CodeJob DescriptionRelavent ExpTotal ExpJob Location
STG-0405209OPC Modeling Manager 
 Candidate should have extensive management experience and background in the patterning / Semiconductor R&D domain. Should have a proven track record of leading cross functional teams in patterning and pattern corrections domain for problem solving. In-depth knowledge and experience of photolithography and reticle enhancement techniques with exposure to 45nm, 32nm and other advanced  technology nodes.  Prior experience with OPC model build, OPC code development and pattern verifications is a big plus.
Qualified candidates must possess a MS/ Ph.D in Computer Science, Electrical Engineering or related fields.
8-12 yrs8-12 yrsBangalore
STG-0317374OPC /ORC Lead                                                                                                                                                                                                                                                Lead a team of Engineers in the OPC/ORC/MRC areas.  Interact with integration and design teams to provide optical proximity corrections on design patterns and improve manufacturability. Lead team to develop new techniques (including scripts & tools) to address technology issues and keyword challenges. 
Candidate should have knowledge in reticle enhancement techniques (RET),  design technology co-optimization  with exposure to 45nm, 32 nm technologies. Ability to interface with lithography, integration and design teams. Knowledge of physical design, layout, and routing is desirable.
Strong leadership skills with technical depth required, experience with global teams a pig plus.
Experience with physical verification tools such as Mentor Calibre SVRF, Cadence Assura, and/or Cadence Virtuoso.  C / C++ coding and shell / tcl / Perl scripting, object oriented programming a plus. 
8-10yrs8-10yrsBangalore
STG-0317374OPC/ORC Engineer                                                                                                                                                                                                                               Interact with integration and design teams to provide optical proximity corrections on design patterns and improve manufacturability. Lead team to develop new techniques (including scripts & tools) to address technology issues and keyword challenges. 
Candidate should have knowledge in reticle enhancement techniques (RET),  design technology co-optimization  with exposure to 45nm, 32 nm technologies. Ability to interface with lithography, integration and design teams. Knowledge of physical design, layout, and routing is desirable.
Strong leadership skills with technical depth required, experience with global teams a pig plus.
Experience with physical verification tools such as Mentor Calibre SVRF, Cadence Assura, and/or Cadence Virtuoso.  C / C++ coding and shell / tcl / Perl scripting, object oriented programming a plus.
5-8 yrs5-8 yrsBangalore
STG-0406140Compact Modeling Engineer
 Develop compact models for FETs and passive devices like diodes, resistors, inductors and capacitors
Design testsites and define test programs for RF/DC characterization
 Work closely with globally integrated team of device modelers, technology developers and circuit designers
Requirement & Skills
Ph.D in Electrical Engg. / Physics with specific background in semiconductor devices / modeling or 3+ years experience in device modeling.
Strong background in semiconductor device physics and characterization particularly in silicon platform is required
Familiarity with industry standard BSIM or PSP models is desirable
Experience with EDA tools like Cadence, Spectre, HSpice and ADS
Hands-on experience with RF/DC device testing & characterization tools.
3+yrs3+yrsBangalore
STG-0405574Characterisation Manager
Managing a group of 10+ team with skills in semiconductor technology and design
* PhD with at least 8 years of industry experience in Semiconductor technology development / procossing role
* IBM Global Business Services helps clients solve complex business and technical issues.  We deliver innovative business consulting, process design, systems integration, application management and design.  Our core competencies include deep business process and industry expertise, advanced analytics and research capabilities, comprehensive IT infrastructure knowledge, and the proven ability to implement enterprise solutions that deliver bottom-line business value. Join a leader. Consult with us.
* Knowledge Seiconductor technology, devices.



8-10 yrs8-10 yrsBangalore





Job CodeJob DescriptionRelavent ExpTotal ExpJob Location
STG-0379087System Validation Engineer
Validation engineer responsible for processor, memory & system level characterization of IBM Servers. Candidates should have strong fundamentals in processor, memory, system architecture concepts. Perform Frequency, Power characterization of processors and systems. System level debug, silicon bring up, hands on experience in a lab is required. Programming skills in C/C++, Perl desired.
· Excellent communication skills (Oral & Written) & 
· Ability to work with a global team. 
· Ability to work in a matrixed organization with high attention to detail is essential.
0-6 yrs0-6 yrsBangalore
STG-0379087Performance Analysis Engineer
Software Tools development for Performance analysis tools. Develop tools, run traces, analyze debug failures. Engage / interface with verification, validation and characterization teams to run content on simulation and real hardware for data collection, triage and debug. 
Skills Required: C++/C, Perl, programming. Understanding of microprocessor architecture, micro-architecture and system level understanding. 
· Excellent communication skills (Oral & Written) 
· Willingness and ability to work with cross functional global teams with aggressive schedules. 
0-6 yrs0-6 yrsBangalore
STG-0377327Validation Tools Development Engineer
Validation Tools Development Engineer will be responsible for the development of tools targeting microarchitecture features - Caches, Execution Pipelines, Interrupts, TLB's etc. Candidate will also have the opportunity to work on processors that are changing the landscape of Servers & Gaming Systems in the industry. Candidates should have strong Microprocessor Architecture knowledge, system architecture, Post silicon Validation domain expertise and simulation techniques. Software design and development skills using C/Assembly programming, C, C++, Assembly, OS Internals (Linux or similar), Knowledge of Test (planning, coverage, deliverables), Desirable: Strong scripting experience with perl /ksh/ python. Familiarity / experience in logic simulation (event & cycle based) & logic design. Having worked on hardware/software bring up in a Lab.
· Excellent communication skills (Oral & Written) 
· Willingness and ability to work with cross functional global teams with aggressive schedules.
0-6 yrs0-6 yrsBangalore






Job CodeJob DescriptionRelevant ExpTotal ExpJob Location
STG-0390330Custom Digital Circuit Designer -                                                                                                                                                                                                                                                                     
Educational Background: BE/BTech/MTech in ECE/EE/CSE
Job Description:
As a custom digital design engineer, you are responsible for schematic realization of RTL ( VHDL ) and entire physical design of complex high speed digital blocks
Must have deep knowledge CMOS digital circuit fundamentals and VHDL. Be able to analyze transistor level circuits for critical paths.  
Must have hands on experience in physical design of digital circuits from synthesis, placement, routing. Hands on experience with physical verification, timing closure and signal integrity closure for digital blocks implementation. 
Ability to adopt to new technologies and tools/flows is a must.
4+years4+yearsBangalore
STG-0394754Physical design Engineer                                                                                                                                                                                                                  
Educational Background: BE/BTech/MTech in ECE/EE/CSE 
Job responsibilities include physical implementation of high speed digital blocks from RTL through physical verification  .Must have strong CMOS digital circuit fundamentals. Be able to analyze transistor level circuits for critical paths.  Must have hands on experience in physical design of digital circuits from synthesis, placement, routing. Hands on experience with physical verification, timing closure and signal integrity closure for large block level designs. Ability to adopt to new technologies and tools/flows is a must.  Familiarity to VHDL, SPICE, Schematic entry will be added advantage.
 3+ years 3+ yearsBangalore
STG-0394754Senior Physical Design Engineer
Looking for professionals with hands on Physical Design experience ( ASICs, ASPs, Processors ). The Job involves handling high performance unit level integration for processor chip.  Responsibilities include, floorplanning, planning signal wires, pushing the data into lower level macros,  physical integration of the lower level abstracts at the next higher level, timing closure, clean up signal and design integrity issues,  physical verification and complete delivery of the high quality integrated unit to the chip level. Hands on exposure to timing closure techniques is a must.  This role Involves working with global PD and timing leads, Logic Designers, PD engineers and project managers in a matrix organization.  Individual must have hands on PD experience with industry standard tools.  Exposure to Cadence virtuoso tool will be added advantage. Candidates with Processor implementation back ground are preferred. Looking for candidates with more than 6 years of relavent PD experience. This role Involves working with global PD and timing leads, Logic Designers, PD engineers and project managers in a matrix organization.  Individual must have hands on PD experience   with industry standard tools.   Exposure to Cadence virtuoso tool will be added advantage. Candidates with Processor implementation back ground are preferred.
6 + years6 + yearsBangalore
STG-0390330 Sr Timing Engineer Experience :  
 Job Description :Looking for professionals with hands on chip level timing experience ( ASICs, ASPs, Processors ). The Job involves handling timing analysis and closure of complex units of high performance processor chip.  
Candidate must have, deep knowledge of clocks, process variations, process variations and concepts of floorplanning, physical and logical optimization 
Must of hands on experience with timing closure of complex chips, blocks,  timing constraints development, timing budget creations, timing analysis and closure of hierarchical blocks. Scripting using TCL and Perl is required 
This role Involves working with global timing and PD leads as well as Logic Design and PD engineers and project managers in a matrix organization.  Individual must have hands on PD and timing  experience with industry standard tools. Shall be willing to learn new tools and methodologies 
Candidates with Processor implementation back ground are preferred.
6 + years6 + yearsBangalore
STG-0394752Memory Cicuit Design Engineer :                                                                                                      
Candidate is responsible for design of high performance memory arrays for processor applications. The candidate would have deep experience in transistor level circuit design including construction of critical paths, margins analyses using spice like tools,  intimate familiarity of extracts and layouts. Candidate should have sound knowldege of  IP Characterization flows for  timing, power and reliability . A good understanding of logic and physical verificaiton flows is highly preferred. 
Must have hands on experience in register file, SRAM circuit designs. Be able to handle multiple projects, priorities and be willing to work in a matrix organization. Strong leadership qualities are a must for senior positions , Memory ( Register File and SRAM ).
8+ years8+ yearsBangalore
STG-0394757Verification Team Member                                                                                                                                                                                                                            C++ programming skills essentil.  Will contribute to the development of test plan, verification infrastructure development, verification of complex processor core functions and sign off of the design for tapeout. Will ensure adequate levels of thoroughness and quality in verification. 
Experience in high level verification languages like System Verilog, Specman or Vera is essential.
Must have prior experience building test infrastructure and test cases using C++, System Verilog, Specman or Vera in atleast 3 projects.  
Must have handled the test plan development and contributed to teams doing verification of complex designson multiple projects. 
Must have familiarity with logic designs and micro architecture for complex chips/IPs preferably processor chip/cores. 
Exposure to post-silicon debug and characterization is desirable.
 5 + Years 5 + YearsBangalore
STG-0394757Verification Lead                                                                                                                                                                                                                                                 Will contribute to the development of test plan, verification infrastructure development, verification of complex processor core functions and sign off of the design for tapeout. Will ensure adequate levels of thoroughness and quality in verification. 
Experience in high level verification languages like System Verilog, Specman or Vera is essential.
Must have prior experience building test infrastructure and test cases using C++, System Verilog, Specman or Vera in atleast 3 projects.  
Must have handled the test plan development and contributed to teams doing verification of complex designson multiple projects. 
Must have familiarity with logic designs and micro architecture for complex chips/IPs preferably processor chip/cores. 
Exposure to post-silicon debug and characterization is desirable.
8 + Years8 + YearsBangalore
STG-0394756Verification Manager                                                                                                                                                                                                                                                                                                                                                                              The selected candidates will manage teams responsible for verification of processor cores and ASIC chips and will be directly responsible for the timely delivery as per aligned plans. She/He will also be responsible for monitoring and coaching the team, handling teaming and inter personal issues, appraisals, salary planning and the strategic development of the team. The candidates must have good level of experience in managing teams of sizes exceeding8 for 4-5 years. The candidate must also have experience in leading teams working on IP/SOC or Processor Core Verification and must have been accountable for the schedule and quality of the deliverables. Must have adequate understanding of Verification Flows tools and methodologies. Previous experience working on verification and /or logic design in technical roles is highly desirable.                                                                                                                               Must have very good experience on people management including career planning, rating, ranking, salary planning, teaming and motivation. on must love to work with people to solve complex technical problems. 8 – 15yrs 8 – 15yrsBangalore











Job CodeJob DescriptionRelavent ExpTotal ExpJob Location
STG-0406267ASIC Layout Designer                                                                                                                                                                                                                                                                                                            
Layouts of the circuits/ sub-circuits would include Receivers, ADC ,VR,Comparators,LVDS, PLL....etc with floor planing knowledge macro/block wise.etc . Run all necessary Physical Design (PD) rule checks like DRC, LVS, Meth, ESD,ERC,IR,EM..etc. using industry standard tools like Calibre,Hercules...etc.Knowledge of layout methodogies like Cross-Coupling, Common Centroid, Mirroring, Interdigitation for Analog layouts.
VLSI circuit layout using industry leading tools, in particular CADENCE Virtuoso XL with technology nodes 65nm and below . 
Responsible for a number of custom layouts which meet timing, power, noise and electromigration requirements .
layout verification methodologies, and design for yield and manufacturability . Ability to write CADENCE “SKILL”  programming ,Perl is a plus . 
Basic understanding of CMOS technology and devices .CMOS Circuit Design knowledge would be advantageous . 
 Ability to work in an international team and a dynamic environment .Ability to learn and adapt to new tools and methodologies . 
 Excellent communication and teamwork skills and good English is required .Star RC layout extraction knowledge is a plus. 
Work in a Team with Circuit Designer, Integrator and Timing Lead . Optimize Interconnections (Resistivity, Capacitance) for area and delay. 
Optimize design for Yield and Manufacturability . “Skill” programming for enhanced layout productivity . 
Deliver all cadence design data according to schedule in required quality.
 .
6 yrs6 yrsBangalore
STG-0406268Circuit design engineer:
Candidate will be responsible for circuit design and verification of high speed SerDes IP blocks.b/ Work with digital/ Analog / layout designers across various global sites, to integrate the IP block
Skills and Qualifications:
B.Tech, MTech/MS with atleast 0- 4years of circuit design blocks implementation experience 
Must have strong analog circuit design knowledge and hands on experience in transistor level design, layout and design closure
Candidate should be have good experience in design of analog macros like, Amplifiers, Voltage regulators, Data converters, PLL high speed serial driver, receiver design.Candidate should have in-depth understanding of couple of macros, and hands on experience in taking the analog macro's design from spec to GDS.Hands on experience with Cadence Spectre, APS, Virtuoso, Star RC extraction tools, Strong communication skills ( oral and written ) and be a strong team player,Good Signal integrity ( EM, IR Drop, and xtalk ) understanding. Be able to analyze and fix the violations
 Good scripting and automation skills ( perl, tcl ) would be added advantage,Exposure to Serdes, DDR3, .
PCIe and architecture experience on IPs for real products would be an added advantage.
0- 4years0- 4yearsBangalore
STG-0406262Senior Physical/ASIC Design  Engineer                                                                                                                                                                                                                                                                      :Looking for professionals with hands on Physical Design experience ( ASICs, ASPs, Processors ). The Job involves handling high performance unit level integration for processor chip. Responsibilities include, floor planning, planning signal wires, pushing the data into lower level macros,  physical integration of the lower level abstracts at the next higher level, timing closure, clean up signal and design integrity issues,  physical verification and complete delivery of the high quality integrated unit to the chip level. Hands on exposure to timing closure techniques is a must.  This role Involves working with global PD and timing leads,PD engineers and project managers in a matrix organization.  Individual must have hands on PD experience with industry standard tools.  Exposure to Cadence virtuoso tool will be added advantage.                                                             Candidates with Processor implementation back ground are preferred.6 yrs6 yrsBangalore
STG-0406264Logic Designer                                                                                                                                                                                                                                                                                               Our engineers work on logic Design, Synthesis, Front End Processing on IBM's leading edge IPs - High Speed SerDes & DDR3 Phy, as well as complex System ASICs. The position requires solid understanding of logic design for complex designs involving analog and digital parts, hands on coding experience using VHDL/Verilog/RTL, experience with EDA tools on Synthesis, FEP, Boolean Equivalence checks & Timing closure. Scripting knowledge with Perl will be a plus.  this is a old one but would should work .2-10 yrs2-10 yrsBangalore
STG-0406265Verification Lead                                                                                                                                                                                                                                                                                                                      Implement verification plans to verify unit level, sub-system and core / chip level functionality. Define, architect and build a robust and re-usable verification environment for the core / chip.Solid understanding of VHDL / Verilog based RTL designs. Verification coding experience in System Verilog with OVM knowledge with good debugging expertize. Work closely with design engineers to ensure adequate functional and code coverage, and create fully random based testbench and testcases. Preference given to candidates with formal verification experience. BTech, M Tech/MS with minimum 5-7 years experience (atleast 2 yrs in a leadership role). 2 years experience with System Verilog / Vera / Specman Constrained Random test-bench knowledge.1 year experience with Assertion-Based Verification (SVA, PSL).                                              5-7 yrs5-7 yrsBangalore




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