AMD | Hardware/Physical Design | Hyderabad

AMD Hyderabad, India,

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JobDescription:

A. Job Reference: HARDWARE/PHYSICAL DESIGN

Education: Engineering Degree

Exp: Minimum 4+ year

Position: Senior Design Engineer

No of Positions: 12

1. Physical Design

Key Responsibilities

The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs. Fusion programs will cater to the next gen compute requirements bringing in CPU, GPU, MC, Video and other misc functions on an integrated monolithic die. In this position you will be responsible for the entire Physical implementation of our chips designed for PC, Handheld, Entertainment or DTV requirements. This position requires interface with large front-end design teams in US, Canada and India, mentoring new hires and owing an entire chip from inception to tapeout.

The Sr. Physical Design Engineer will be responsible for 1. some full chip activities covering floorplanning, clocking, budgeting, timing, verification etc., and/or 2. block level physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks, power delivery solution development etc. In addition to this, he/she will also be participating in Physical design Flow development/upgrade by continuously working with the internal design teams and CAD vendors.

The following is desirable:
 Effective written and oral communication skills in English
 Understanding Verilog HDL
 Understanding Deep Submicron effects such as 90nm and below
 Understanding OCV, DFM, DFY
 Excellent Block level and Fullchip level Timing closure skills
 Displaying motivation, leadership skills and working in teams


Job Requirements:

 Minimum 4 year of ASIC physical design experience.
 Reasonable Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
 Hands on experience and reasonable knowledge in Cadence and Synopsys Physical Implementation Tools
 Should have participated in a minimum of 3-4 fullchip tapeouts.
 Scripting Language with PERL, TCL, AWK, shell scripting is highly desirable.
 Familiar with Physical Verification will be a plus.


B. Job Reference: HARDWARE/Physical DESIGN

Education: Engineering Degree

Exp : Minimum 6+ year

Position: Staff Engineer

No of Positions: 4

1.Physical Design

Key Responsibilities

The position is for a PD staff engineer in the AMD PSE PD group catering to building the next generation fusion SoCs. Fusion programs will cater to the next gen compute requirements bringing in CPU, GPU, MC, Video and other misc functions on an integrated monolithic die. The candidate will technically lead and mentor a team of engineers on Physical Design (place and route ) duties both on block, as well as global top-level activities, which includes: top-level floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis, ECO tasks (timing, functional, noise based ECOs), power delivery etc. Good understanding required of all aspects of physical design taking a design from RTL/Netlist to GDSII and production. In addition the candidate is expected to have close to expert level of skill in a few core areas.

The candidates responsibilities will also include flow and methodology development related to the above tasks or new tasks that arise as technology changes. This involves flow design and implementation via coding in various languages. In addition, very strong communication skills and an ability to work in large groups are essential to being successful.

Excellent debugging skills is a must, candidate must be more than a tool executor, and knows how to diagnose and devise workarounds for problems.

Requirements

Minimum 6 years of ASIC physical design experience.
Leadership and Mentoring skills a must.
Strong Back ground of ASIC Physical Design : Floor planning , P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
Hands on experience and detailed knowledge in Cadence or Synopsys or Magma ASIC Physical Design Tools
Scripting Language with PERL ,TCL,AWK, shell scripting a very big asset.
Familiar with Physical Verification is also desirable.


Thanks & Regards

Rajasekhar.R
rajasekhar@techpointsolutions.com